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ASPLOS 2019 / accelerator storage

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration

Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal C. Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, and Joel S. Emer

Diagram of the buffet storage interface and its implementation
Buffet interface and implementation for decoupled accelerator storage.

Accelerators often implement custom on-chip buffering logic that is difficult to reuse. Buffets define a small storage abstraction that can be composed across accelerator designs.

Custom buffers consume design effort and bind storage behavior to one accelerator. Buffets provide decoupled fills and accesses, fine-grained synchronization, hierarchical composition, and multicast behind a reusable interface. An RTL implementation adds roughly 2% control overhead to an 8 KB RAM. Across several workloads, the design improves energy-delay product compared with DMA-managed double buffering and caches.